Optimising financial computation for reconfigurable hardware

This thesis proposes novel methodologies for design, optimisation and generalisation of reconfigurable hardware based finance computation. The applications of the proposed methodologies to numerical methods which are commonly used in the finance industry, such as Monte Carlo and Finite difference are studied in detail. These studies show reconfigurable hardware can effectively improve performance and energy efficiency in finance computation. There are three contributions. First, an application independent Monte Carlo framework for interest rate derivatives payoff evaluations based on the HeathJarrowMorton (HJM) mathematical Framework. By identifying three levels of functional specialisations in the model, the framework is able to retain good performance while supporting multiple applications. In addition, a process is proposed for the Monte Carlo framework to identify the optimal reduced precision data representation, in order to utilise hardware resource better and retain output numerical accuracy. The automatically generated Field-Programmable Gate Array (FPGA) implementations show significant speedup and energy saving over comparable Central Processing Unit (CPU) and Graphical Processing Unit (GPU). Second, a novel framework for accelerating option payoff evaluation based on finite difference method. The parallelism of the proposed architectures is exploited based on two levels of computational granularities. The implementations are generated based on a high level description. Significant speedup and energy savings are archived comparing our FPGA designs over both CPU and GPU designs. Third, a novel performance optimisation process based on dynamic reconfiguration for stencil computation. By optimally adjusting the underlying numerical procedure and making use of carefully chosen coefficients for constant multipliers, both the hardware resource consumption per kernel and the amount of computation needed per problem are reduced, and the numerical accuracy requirements are also met. Significant speedup is shown by comparing the optimised dynamic design with the unoptimised dynamic design and the original static design.